This relates generally to integrated circuits and more particularly, to programmable integrated circuits.
Programmable integrated circuits are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design tools to design a custom logic circuit. When the design process is complete, the computer-aided design tools generate configuration data. The configuration data is loaded into memory elements on a programmable integrated circuit to configure the device to perform the functions of the custom logic circuit. Such types of programmable integrated circuits are sometimes referred to as a field-programmable gate array (FPGA).
An FPGA typically includes logic circuitry having lookup tables (LUTs), adders, and registers that are configurable to allow a user to customize the logic circuitry according to the user's particular needs. The logic circuitry is organized into an array of logic regions sometimes referred to as logic array blocks (LABs). In addition to the logic circuitry, an FPGA also includes large memory blocks for storing user data and digital signal processing (DSP) blocks that are partly or fully hardwired to perform one or more specific tasks such as a mathematical operation. In addition to the configurable logic, memory, and DSP blocks, an FPGA also includes programmable routing fabric that is used to interconnect the LABs with the memory and DSP blocks. The combination of the programmable logic and routing fabric is sometimes referred to as “soft” logic. The DSP blocks are sometimes referred to as “hard” logic.
The performance of an FPGA is limited by the longest signal propagation delay through a combinational logic path between two sequential digital flip-flop circuits. Conventionally, an FPGA is implemented as a single integrated circuit die. In such scenarios, there will often be a long combinational logic path that starts in a first LAB, traverses an unused memory block or DSP block, and ends in a second LAB, which sets the critical path for the FPGA. This particular architecture can substantially limit the performance of the FPGA.
It is within this context that the embodiments described herein arise.